In modern integrated circuits (ICs), the flip-flops contribute to a substantial portion of any circuit design's power consumption. A comparison of the power consumption by the various units in an IC is as follows; logic implementation 29%, flip flops 27%, RAM 18%, clock tree 16% and the integrated clock gating (ICG) consumes 10% of the total power in a typical design. Therefore in an IC, the significant power consumption is due to tedious synchronization of the various clock phases and routing of the clock signals. The majority of power inside a flip flop is consumed by the transistors receiving the clock input, since the data activity factors are typically much lower. Irrespective of whether the data changes every cycle or not, the transistors receiving the clock input keep switching at every clock cycle. Thus, it is apparent that with reduced transistor switching, the power consumed by the flip-flop can also be reduced. Further, constant toggling of the clock input causes a significant amount of gate capacitances. It is apparent that with the reduction in the number gate capacitances, a considerable amount of power consumed by the flip-flop in the IC can be reduced.